Conical-Shaped or Tier-Shaped Pillar Connections

ABSTRACT

A pillar structure, and a method of forming, for a substrate is provided. The pillar structure may have one or more tiers, where each tier may have a conical shape or a spherical shape. In an embodiment, the pillar structure is used in a bump-on-trace (BOT) configuration. The pillar structures may have circular shape or an elongated shape in a plan view. The substrate may be coupled to another substrate. In an embodiment, the another substrate may have raised conductive traces onto which the pillar structure may be coupled.

This application is a continuation application of U.S. patentapplication Ser. No. 13/449,078, filed on Apr. 17, 2012, entitled“Conical-Shaped or Tier-Shaped Pillar Connections,” which application isincorporated herein in its entirety.

BACKGROUND

Generally, semiconductor dies comprise active devices, metallizationlayers forming connections to the active devices, and I/O contacts toprovide the metallization layers (and active devices) signals and power.The metallization layers generally comprise a series of dielectriclayers and metal layers in order to provide all of the requiredconnections between the active devices and the I/O contacts (and betweenindividual active devices). These dielectric layers may be formed fromlow-k dielectric materials with dielectric constants (k value) betweenabout 2.9 and 3.8, ultra low-k (ULK) dielectric materials, with k valuesless than about 2.5, or even extra low-k (ELK) dielectric materials withk values between about 2.5 and about 2.9, or some combination of low-kdielectric materials.

However, while these low-k, ULK, and ELK materials may be used toimprove the electrical characteristics of the metallization layers andthereby increase the overall speed or efficiency of the semiconductordevice, these materials may also exhibit structural deficiencies. Forexample, some of these materials may have greater trouble than otherdielectric materials handling the stresses applied to them in thesemiconductor device. As such, the low-k, ULK, and ELK materials tend todelaminate or crack when too much pressure is applied to the low-K, ELK,and ULK materials, thereby damaging or destroying the semiconductordevice and reducing yields and increasing costs.

These delamination issues related to stress can be particularlytroublesome when using packaging techniques such as surface-mounttechnology (SMT) and flip-chip packaging. As opposed to moreconventional packaged integrated circuits (ICs) that have a structurebasically interconnected by fine gold wire between metal pads on the dieand electrodes spreading out of molded resin packages, these packagingtechniques rely on bumps of solder to provide an electrical connectionbetween contacts on the die and contacts on a substrate, such as apackaging substrate, a printed circuit board (PCB), another die/wafer,or the like. The different layers making up the interconnectiontypically have different coefficients of thermal expansion (CTEs). As aresult, additional stress derived from this difference is exhibited onthe joint area, which also may cause cracks to form and/or delamination.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the embodiments, and the advantagesthereof, reference is now made to the following descriptions taken inconjunction with the accompanying drawings, in which:

FIGS. 1-7 illustrate intermediate stages in forming a semiconductordevice having a conical shaped pillar structure in accordance with anembodiment;

FIGS. 8A and 8B illustrate a first substrate connected to a secondsubstrate using a conical shaped pillar in accordance with anembodiment;

FIGS. 9-12 illustrate intermediate stages in forming a semiconductordevice having a tiered pillar structure in accordance with anembodiment;

FIGS. 13-15 illustrate various shapes of tiered pillar structures inaccordance with embodiments; and

FIGS. 16A-16E illustrate various shapes in a plan view of pillarstructures in accordance with various embodiments.

DETAILED DESCRIPTION

The making and using of embodiments are discussed in detail below. Itshould be appreciated, however, that this disclosure provides manyapplicable inventive concepts that can be embodied in a wide variety ofspecific contexts. The specific embodiments discussed herein are merelyillustrative of specific ways to make and use the embodiments, and donot limit the scope of the disclosure.

Embodiments described herein relate to the use of bumps or balls(collectively referred to herein as bumps) for use with interconnectingone substrate with another substrate, wherein each substrate may be anintegrated circuit die, an interposer, packaging substrate, printedcircuit board, organic substrate, ceramic substrate, high-densityinterconnect, and/or the like. As will be discussed below, embodimentsare disclosed that utilize a pillar and/or a bump having a smaller tipsection relative to a base section, such as a conical or tiered shape.It has been found that embodiments such as those discussed herein mayreduce delamination issues as well as reducing bridging between adjacentconnections, thereby increasing throughput and reliability. Theintermediate stages of a method for forming a conical or tiered shapepillar and/or bump are disclosed herein. Embodiments such as these maybe suitable for use in flip-chip configuration, three-dimensional (3D)IC or stacked die configurations, and/or the like. Throughout thevarious views and illustrative embodiments, like reference numbers areused to designate like elements.

FIGS. 1-7 illustrate various intermediate stages of a method of forminga semiconductor device having a pillar and/or bump having a conicalcross-sectional shape in accordance with an embodiment. Referring firstto FIG. 1, a portion of a substrate 100 is shown in accordance with anembodiment. The substrate 100 may comprise, for example, bulk silicon,doped or undoped, or an active layer of a semiconductor-on-insulator(SOI) substrate. Generally, an SOI substrate comprises a layer of asemiconductor material, such as silicon, formed on an insulator layer.The insulator layer may be, for example, a buried oxide (BOX) layer or asilicon oxide layer. The insulator layer is provided on a substrate,typically a silicon or glass substrate. Other substrates, such asmulti-layered or gradient substrates may also be used. In anotherembodiment, the substrate 100 may comprise a substrate to which anintegrated circuit die may be attached. For example, the substrate 100may be an interposer, a packaging substrate, a high-densityinterconnect, a printed circuit board, another integrated circuit die,or the like.

It should be noted that in some embodiments, particularly in embodimentsin which the substrate 100 is an integrated circuit die, the substrate100 may include electrical circuitry (not shown). In an embodiment, theelectrical circuitry includes electrical devices formed on the substrate100 with one or more dielectric layers overlying the electrical devices.Metal layers may be formed between dielectric layers to route electricalsignals between the electrical devices. Electrical devices may also beformed in one or more dielectric layers. In an embodiment, the substrate100 includes one or more low-k and/or ELK dielectric layers.

For example, the electrical circuitry may include various N-typemetal-oxide semiconductor (NMOS) and/or P-type metal-oxide semiconductor(PMOS) devices, such as transistors, capacitors, resistors, diodes,photo-diodes, fuses, and the like, interconnected to perform one or morefunctions. The functions may include memory structures, processingstructures, sensors, amplifiers, power distribution circuitry,input/output circuitry, or the like. One of ordinary skill in the artwill appreciate that the above examples are provided for illustrativepurposes only to further explain applications of some illustrativeembodiments and are not meant to limit the disclosure in any manner.Other circuitry may be used as appropriate for a given application.

Conductive traces 102 are provided in an upper surface of the substrate100 to provide external electrical connections. It should be noted thatthe conductive traces 102 represent an electrical connection toelectrical circuitry formed on the substrate 100, an electricalconnection to a through-substrate via, a redistribution line, and/or thelike. The conductive traces 102 may comprise a conductive material suchas copper, although other conductive materials, such as tungsten,aluminum, copper alloy, or the like, may alternatively be used. Theconductive traces 102 may be formed using a damascene or dual damasceneprocess which may include a copper overfill into an opening followed bythe removal of the excess copper through a process such as chemicalmechanical polishing (CMP). However, any suitable material (such as,e.g., aluminum) and any suitable process (such as deposition andetching) may alternatively be used to form the conductive traces 102.

Embodiments such as those disclosed herein may be particularlybeneficial in a system using bump-on-trace (BOT) technology. Generally,these techniques provide for a bump to be coupled directly to theconductive traces (such as conductive traces 852 of the second substrate850 illustrated in FIG. 8). A solder resist may be used to protect otherportions of the trace and/or other traces.

One or more passivation layers, such as passivation layer 104, areformed and patterned over the substrate 100 to provide an opening overthe conductive traces 102 and to protect the underlying layers fromvarious environmental contaminants. The passivation layer 104 may beformed of a dielectric material, such as PE-USG, PE-SiN, combinationsthereof, and/or the like, by any suitable method, such as CVD, PVD, orthe like. In an embodiment, the passivation layer 104 has a thickness ofabout 10,000 Å to about 15,000 Å. In an embodiment, the passivationlayer 104 comprises a multi-layer structure of 750 Å of SiN, 6,500 Å ofPE-USG, and 6,000 Å of PE-SiN.

A protective layer 106 formed and patterned over the passivation layer104. The protective layer 106 may be, for example, a polyimide materialformed by any suitable process, such as spin coating of a photoresister, or the like. In an embodiment, the protective layer 106 has athickness between about 2.5 μm and about 10 μm.

One of ordinary skill in the art will appreciate that a single layer ofconductive/bond pads and a passivation layer are shown for illustrativepurposes only. As such, other embodiments may include any number ofconductive layers and/or passivation layers. Furthermore, it should beappreciated that one or more of the conductive layers may act as a RDLto provide the desired pin or ball layout.

Any suitable process may be used to form the structures discussed aboveand will not be discussed in greater detail herein. As one of ordinaryskill in the art will realize, the above description provides a generaldescription of the features of the embodiment and that numerous otherfeatures may be present. For example, other circuitry, liners, barrierlayers, under-bump metallization configurations, and the like, may bepresent. The above description is meant only to provide a context forembodiments discussed herein and is not meant to limit the disclosure orthe scope of any claims to those specific embodiments.

Referring now to FIG. 2, a conformal seed layer 210 is deposited overthe surface of the protective layer 106 and the exposed portions of theconductive traces 102. The seed layer 210 is a thin layer of aconductive material that aids in the formation of a thicker layer duringsubsequent processing steps. In an embodiment, the seed layer 210 may beformed by depositing a thin conductive layer, such as a thin layer ofCu, Ti, Ta, TiN, TaN, or the like, using chemical vapor deposition (CVD)or plasma vapor deposition (PVD) techniques. For example, in anembodiment, the seed layer 210 is a composite layer including a layer ofTi deposited by a PVD process to a thickness of about 500 Å and a layerof Cu deposited by a PVD process to a thickness of about 3,000 Å. Othermaterials, processes, and thicknesses may be used.

The embodiment illustrated in FIG. 2 illustrates an intermediate step informing a BOT configuration in which a pillar structure, e.g., includinga seed layer (if any) and a pillar, is formed directly on the trace. Insuch an embodiment, an under-bump metallization (UBM) layer may beomitted. In other embodiments, however, additional layers and/or UBMstructures may be utilized.

FIG. 3 illustrates a first patterned mask 312 formed over the seed layer210 in accordance with an embodiment. The first patterned mask 312 willact as a mold for forming conductive pillars in subsequent processingsteps. The first patterned mask 312 may be a patterned photoresist mask,hard mask, and/or the like. In an embodiment, a photoresist material isdeposited and patterned to form openings 314.

It should be noted that the embodiment illustrated in FIG. 3 utilizessloped sidewalls such that the openings 314 are wider along the bottomof the openings along the seed layer 210 than the top portion of theopenings 314, thereby resulting in a conical shape. The tapered profilemay be created by any suitable technique, such as the use of multiplephotoresist layers with different patterning properties and one or moreexposures, diffusion techniques, an image reversal process, multipleexposures using different masks, and/or the like.

Thereafter, conductive pillar 416 is formed in the openings 314 (seeFIG. 3) as illustrated in FIG. 4. The conductive pillar 416 comprisesone or more conductive materials, such as copper, tungsten, otherconductive metals, or the like, and may be formed, for example, byelectroplating, electroless plating, or the like. In an embodiment, anelectroplating process is used wherein the wafer is submerged orimmersed in the electroplating solution. The wafer surface iselectrically connected to the negative side of an external DC powersupply such that the wafer functions as the cathode in theelectroplating process. A solid conductive anode, such as a copperanode, is also immersed in the solution and is attached to the positiveside of the power supply. The atoms from the anode are dissolved intothe solution, from which the cathode, e.g., the wafer, acquires, therebyplating the exposed conductive areas of the wafer, e.g., exposedportions of the seed layer 210 within the openings 314.

FIG. 5 illustrates formation of an optional conductive cap layer 518formed over the conductive pillar 416. As described in greater detailbelow, solder material will be formed over the conductive pillar 416.During the soldering process, an inter-metallic compound (IMC) layer isnaturally formed at the joint between the solder material and theunderlying surface. It has been found that some materials may create astronger, more durable IMC layer than others. As such, it may bedesirable to form a cap layer, such as the conductive cap layer 518, toprovide an IMC layer having more desirable characteristics. For example,in an embodiment in which the conductive pillar 416 is formed of copper,a conductive cap layer 518 formed of nickel may be desirable. Othermaterials, such as Pt, Au, Ag, combinations thereof, or the like, mayalso be used. The conductive cap layer 518 may be formed through anynumber of suitable techniques, including PVD, CVD, ECD, MBE, ALD,electroplating, and the like.

FIG. 6 illustrates formation of solder material 620 and an IMC layer622. In an embodiment, the solder material 620 comprises SnPb, a high-Pbmaterial, a Sn-based solder, a lead-free solder, a SnAg solder, a SnAgCusolder, or other suitable conductive material. FIG. 6 illustrates anembodiment in which the solder material 620 is formed while the firstpatterned mask 312 is present and exhibits a conical shape similar tothe underlying conductive pillar 416. In other embodiments, the soldermaterial 620 (or other suitable material) may be placed on theconductive pillars after removal of the first patterned mask 312.

FIG. 7 illustrates the removal of the first patterned mask 312 (see FIG.3) in accordance with an embodiment. In an embodiment in which the firstpatterned mask 312 is a photoresist mask, a plasma ashing or wet stripprocess may be used to remove the first patterned mask 312. The exposedportions of the seed layer 210 may be removed by, for example, a wetetching process. Optionally, a wet dip in a sulfuric acid (H₂SO₄)solution may be used to clean the wafer and remove remaining photoresistmaterial. A reflow process may be performed, which may cause the soldermaterial 620 to have a rounded shape.

The conductive pillar 416 and, optionally, the conductive cap layer 518form a conductive bump 724 having a conical shape such that sidewalls ofthe conductive bump 724 are tapered. In this situation, a width of thebase portion W_(B) is greater than a width of the tip portion W_(T). Therelatively wide base dimension may reduce current density and thenarrower top portion may reduce the probability of misalignment whencoupling the first substrate 100 to another substrate.

A ratio of the width of the tip portion W_(T) to the width of the baseportion W_(B) may be adjusted for a particular purpose or application.For example, in an embodiment, the ratio of W_(T) to W_(B) may be fromabout 0.5 to about 0.99. In another embodiment, the ratio of W_(T) toW_(B) may be from about 0.6 to about 0.98. In another embodiment, theratio of W_(T) to W_(B) may be from about 0.7 to about 0.93. In anotherembodiment, the ratio of WT to WB may be from about 0.75 to about 0.92.In another embodiment, the ratio of WT to WB may be from about 0.75 toabout 0.97.

FIGS. 8A and 8B illustrate joining two substrates in accordance with anembodiment, wherein FIG. 8A is a side view and FIG. 8B is a perspectiveview. The first substrate 800, represents a substrate such as thesubstrate 100 discussed above with reference to FIGS. 1-7, wherein likereference numerals refer to like elements. The second substrate 850represents a substrate to be attached to the first substrate 800 and maybe an organic substrate, a PCB, a ceramic substrate, integrated circuitdie, an interposer, a packaging substrate, a high-density interconnect,or the like.

The second substrate 850 includes conductive traces 852 formed thereon.The conductive traces may be formed of any suitable conductive material,such as copper, tungsten, aluminum, silver, combinations thereof, or thelike. It should be noted that the conductive traces 852 may be a portionof redistribution layer. As illustrated in FIGS. 8A and 8B, the soldermaterial 620 of the first substrate 100 is brought into contact with theconductive trace 852 and a reflow process is performed. Due to theconical shape of the pillar 416 and/or solder material 620, the soldermaterial may be brought into direct contact with the raised conductivetraces 852 while reducing the risk of bridging between adjacent ones ofthe conductive traces 852.

FIGS. 9-12 illustrate another embodiment in which a tiered pillar isutilized. FIGS. 9-12 illustrate another embodiment in which amulti-tiered pillar structure is formed, rather than a single-tieredpillar structure illustrated in FIGS. 8A and 8B. The multi-tiered pillarstructure of FIGS. 9-12 may be connected to the second substrate (seeFIGS. 8A and 8B) by replacing the single-tiered pillar structure ofFIGS. 8A and 8B. Referring first to FIG. 9, there is shown a structuresimilar to that discussed above with reference to FIG. 3, wherein likereference numerals refer to like elements, except that the firstpatterned mask 312 is replaced with a first tier patterned mask 912 thatis formed and patterned to form a first tier of a pillar structure inopenings 914 as explained in greater detail below.

Referring now to FIG. 10, there is shown a first tier pillar structure1010 formed in the openings 914. In this embodiment, the first tierpillar structure 1010 is formed to an upper surface of the first tierpatterned mask 912. The first tier patterned mask 912 and the first tierpillar structure 1010 of FIG. 10 may be formed in a similar manner usingsimilar processes and similar materials as those used to form the firstpatterned mask 312 and the conductive pillar 416 of FIG. 3. Aplanarization process, such as a CMP process may be used to removeexcess material.

FIG. 11 illustrates a second tier patterned mask 1112 formed over thefirst tier patterned mask 912. The second tier patterned mask 1112 maybe formed in a similar manner using similar processes and similarmaterials as those used to form the first tier patterned mask 912. FIG.11 further illustrates a second tier pillar structure 1114 formedoverlying the first tier pillar structure 1010.

It should be noted, however, that two tiers are illustrated in thisembodiment for illustrative purposes only and that other embodiments mayutilize more tiers. After forming the uppermost tier pillar structure,such as the second tier pillar structure 1114, the first tier patternedmask 912 and the second tier patterned mask 1112 may be removed, therebyresulting in the pillar structure as illustrated in FIG. 12.

As illustrated in FIG. 12, the first tier pillar structure 1010 and thesecond tier pillar structure 1114 form a step pattern such that a lowerlevel tier pillar structure (e.g., the first tier pillar structure 1010)has a larger width than an upper level tier pillar structure (e.g., thesecond tier pillar structure 1114). In an embodiment, the first tierpillar structure 1010 has a height H₁ of about 100,000 Å to about600,000 Å, and the second tier pillar structure 1114 has a height H₂ ofabout 50,000 Å to about 600,000 Å.

FIG. 12 illustrates an embodiment in which both tiers of the pillarstructure exhibit tapered edges of a portion of a generally conicalshape. Other embodiments may utilize one or more cylindrical sectionsrather than conical-shaped sections. For example, FIG. 13 illustrates anexample embodiment in which the lower tier and the upper tier exhibit acylindrical shape. The embodiment illustrated in FIG. 13 may be formedusing similar materials and processes as those discussed above, exceptthat the photoresist mask is exposed and developed such that verticalsidewalls are obtained rather than the tapered sidewalls.

In yet other embodiments, a combination of cylindrical shaped tiers andconical shaped tiers may be used. For example, FIG. 14 illustrates anembodiment in which the lower tier exhibits a cylindrical shape and theupper tier exhibits a conical shape. Another embodiment may utilize alower tier having a conical shape and an upper tier having a cylindricalshape as illustrated in FIG. 15.

As discussed above, embodiments may utilize various shapes in a planview, such as those illustrated in FIGS. 16A-16E. These embodimentsinclude elongated shapes, such as those illustrated in FIGS. 16C-16E.Each of these shapes may be used in embodiments having a continuousshape (e.g., FIGS. 1-7) or tiered shape (e.g., FIGS. 8-14).

Embodiments using an oblong or irregular shape may exhibit similarratios as those discussed above along the other axis, e.g., the majorand minor axis.

In accordance with an embodiment, a device comprising a first substrateand a second substrate is provided. The first substrate includes aconductive trace formed thereon with a conductive pillar formed directlyon the conductive trace. The conductive trace exhibits a planar uppersurface and at least a portion of the conductive pillar has a conicalshape. The second substrate includes conductive traces formed thereon,such that an upper surface of the conductive traces is raised above anupper surface of the second substrate. The conductive pillar of thefirst substrate is coupled to the conductive traces on the secondsubstrate.

In accordance with another embodiment, a device is provided. A substratehaving a conductive trace formed thereon is provided. A conductivepillar is coupled to the conductive trace, wherein the conductive pillarhas a plurality of tiers such that an upper tier has a smaller area in aplan view than a lower tier.

In accordance with yet another embodiment, another device is provided. Asubstrate having a conductive trace formed thereon is provided such thatat least a portion of the conductive trace is exposed. A conductivepillar is positioned over the conductive trace, wherein the conductivepillar has one or more tiers, at least one of the one or more tiershaving an elongated shape.

In accordance with yet another embodiment, a method is provided. Themethod includes forming a first mask, the first mask having a firstopening over a conductive trace on a first substrate, forming a firsttier in the first opening, forming a second mask over the first mask,the second mask having a second opening over the first tier, and forminga second tier in the second opening. The method further includesremoving the first mask and the second mask, each of the first tier andthe second tier having a conical shape and a surface of an overlyingtier has a smaller area in a plan view than an adjacent surface of alower tier.

In accordance with yet another embodiment, a method is provided. Themethod includes forming a plurality of tiers, the plurality of tiersforming the connector. Forming each tier of the plurality of tiersincludes forming a mask and forming a tier in the mask. The methodfurther includes removing each mask.

In accordance with yet another embodiment, a method is provided. Themethod includes forming a first mask, the first mask having a firstopening over a conductive trace on a first substrate, forming a firsttier in the first opening, and forming a second tier in the firstopening, the first tier being interposed between the second tier and theconductive trace, wherein the first tier and the second tier are formedof different materials. The method further includes removing the firstmask.

Although the present disclosure and its advantages have been describedin detail, it should be understood that various changes, substitutionsand alterations can be made herein without departing from the spirit andscope of the disclosure as defined by the appended claims. Moreover, thescope of the present application is not intended to be limited to theparticular embodiments of the process, machine, manufacture, andcomposition of matter, means, methods and steps described in thespecification. As one of ordinary skill in the art will readilyappreciate from the disclosure, processes, machines, manufacture,compositions of matter, means, methods, or steps, presently existing orlater to be developed, that perform substantially the same function orachieve substantially the same result as the corresponding embodimentsdescribed herein may be utilized. Accordingly, the appended claims areintended to include within their scope such processes, machines,manufacture, compositions of matter, means, methods, or steps.

What is claimed is:
 1. A method of forming an connector, the methodcomprising: forming a first mask, the first mask having a first openingover a conductive trace on a first substrate; forming a first tier inthe first opening; forming a second mask over the first mask, the secondmask having a second opening over the first tier; forming a second tierin the second opening; and removing the first mask and the second mask,each of the first tier and the second tier having a conical shape and asurface of an overlying tier has a smaller area in a plan view than anadjacent surface of a lower tier.
 2. The method of claim 1, wherein thefirst tier has tapered sidewalls.
 3. The method of claim 2, wherein thesecond tier has tapered sidewalls.
 4. The method of claim 1, wherein thesecond tier has tapered sidewalls.
 5. The method of claim 1, wherein athickness of the first tier is greater than a thickness of the secondtier.
 6. The method of claim 1, wherein the first tier and the secondtier form a conductive pillar, and further comprising attaching theconductive pillar to a raised trace on a second substrate using abump-on-trace.
 7. The method of claim 6, wherein a bump in thebump-on-trace does not extend along sidewalls of the conductive pillar.8. A method of forming an connector, the method comprising: forming aplurality of tiers, the plurality of tiers forming the connector,forming each tier of the plurality of tiers comprising: forming a mask;and forming a tier in the mask; and removing each mask.
 9. The method ofclaim 8, wherein each tier has a conical shape.
 10. The method of claim8, wherein a first surface of an overlying tier contacts a secondsurface of an underlying tier, the first surface being smaller than thesecond surface.
 11. The method of claim 8, wherein a bottommost tier hasa conical shape.
 12. The method of claim 8, wherein an uppermost tierhas a conical shape.
 13. The method of claim 8, wherein an uppermosttier comprises solder.
 14. The method of claim 8, wherein a thickness ofa lower tier is greater than a thickness of an upper tier.
 15. A methodof forming an connector, the method comprising: forming a first mask,the first mask having a first opening over a conductive trace on a firstsubstrate; forming a first tier in the first opening; forming a secondtier in the first opening, the first tier being interposed between thesecond tier and the conductive trace, wherein the first tier and thesecond tier are formed of different materials; and removing the firstmask.
 16. The method of claim 15, wherein each tier of the first tierand the second tier has a conical shape.
 17. The method of claim 15,wherein the second tier comprises solder.
 18. The method of claim 15,further comprising, prior to forming the second tier, forming a thirdtier in the first opening, the third tier being interposed between thesecond tier and first tier, wherein the first tier, the second tier, andthe third tier are formed of different materials.
 19. The method ofclaim 15, attaching the first substrate to a second substrate using abump-on-trace connection, wherein the second tier is connected to araised trace on the second substrate.
 20. The method of claim 15,wherein the first tier and the second tier have an elongated shape in aplan view.